Principal Investigator: Domenic Forte
Start Date: June 1, 2017
End Date: May 31, 2022
Electronic computing hardware forms the foundation of modern information systems and cyber infrastructure. However, the unavoidable involvement of untrusted parties who can insert malicious circuits (i.e., hardware Trojans), steal intellectual property (IP), and produce counterfeits have made hardware more vulnerable to cyber-attacks. National defense, welfare, and economic growth all suffer through 1) weaker security and quality of critical infrastructures; 2) substantial economic and reputational losses for IP owners; 3) increased revenue for terrorist groups, criminals, and adversarial nation states; and 4) lower incentive to innovate and develop new products. The objective of this project is to advance the state-of-the-art in hardware obfuscation for IP protection. Hardware obfuscation refers to transformation of a circuit design into one that is functionally equivalent to the original, but infeasible to reverse engineer and/or obtain unrestricted use without significant effort.
This project targets four major limitations associated with existing hardware obfuscation techniques: 1) Impractical overheads for real-world designs; 2) Susceptibility to attacks; 3) Poor scalability to large circuits of practical interest; and 4) lack of metrics and benchmarks in the research community to objectively compare different methods. Efficiency and scalability are being improved by developing novel circuit entropy metrics and holistic obfuscation algorithms that operate on decision diagrams. Outreach activities dedicated to obfuscation and awareness of IP piracy issues include creation of the first publically available benchmarks, conducting online global competitions, and generating new course materials, projects, and book. Through integration of these activities, measureable improvements in the attack resistance of obfuscated combinational and sequential designs are expected by project’s end.