Development of Universal Security Theory for Evaluation and Design of Nanoscale Devices

Principal Investigator: Mark Tehranipoor

Sponsor: University of Connecticut

Start Date: July 23, 2015

End Date: December 31, 2020

Amount: $2,280,000

Abstract

The MURI project involves the investigation of emerging nanoscale devices from a security perspective. More specifically, the project aims to identify, quantify and materialize security properties that are inherent in emerging nano-devices and integration technologies, so that security can be constructed into a system from a fundamental level and not just as an afterthought. For the August 2015-July 2016 time period, the plan is to fulfill the following:

Composition Heuristics and Modeling: one of the main objectives of this task is to develop a universal heuristic that will allow the design of security primitives (e.g. PUFs, TRNGs, etc.) based on security requirements and metrics. Other than coming up with ad-hoc designs or solutions for different security challenges, this composition heuristic allows the designer to construct security primitives using different security properties of the fundamental elements (e.g. transistors or custom gates) in the design platform. Hence, a key feature of this composition is to create security-oriented abstract models of the elements (e.g. transistors) that incorporate and also optimize security properties and metrics. This abstract model works as the building block of the composition to maximize the outcome of the designed primitive. This composition heuristic, incorporating the abstract model of the composition elements will be a powerful tool for the designer to design security primitives as necessary.

Security Metrics: The metrics used to assess hardware security primitives, attacks and countermeasures so far have focused on output-level quantification. In other words, a majority of the security metrics employed have failed to account for design-level optimization and only provide security measures at later stages where further optimization is unfeasible. Further, pre-existing metrics focus purely on circuit or system-level implementation and thus, quantifying security at the device level has not been considered. The project aims to combine fundamental knowledge of device properties, their composition as a system/security primitive and information theoretical measures to propose novel device-level metrics that can enhance security at the nano- and ultimately, macro-level.

New Security Primitives: The project also aims to investigate new security primitives that can enable novel security applications beyond conventional cryptography and security measures. IN this regard, nanoscale devices are being sought and their features are being leveraged to design new primitives. For example, nanoscale devices such as PCM and memristors coupled with their non-volatility and gradual data retention-loss, can be used to design primitives for anti-counterfeiting, drifting key mechanisms, and resistance against replay attacks. In addition, other emerging nanoelectric devices and technologies, such as graphene and carbon nanotubes, have potential capabilities to enhance pre-existing primitives as well as deliver novel countermeasures to various attacks. For example, the ability to create printable circuits with graphene on flexible substrate, and creating ultra-low power circuits, and bio-chemical sensors using CNTs can potentially elevate supply chain security and IoT security. Furthermore, these nanoscale devices can be utilized to counter currently existing challenges such as reliability, footprint reduction, and available entropy for security primitives such as PUFs and TRNGs.