SHF: Small: Design-for-Debug Architecture for Post-Silicon Security Validation

Principal Investigator: Prabhat Mishra

Sponsor: National Science Foundation

Start Date: November 1, 2019

End Date: September 30, 2022

Amount: $499,973


System-on-Chip (SoC) is the brain behind computing and communication in a wide variety of systems, starting from simple electronic devices in smart homes to complex navigation systems in airplanes. SoCs are designed today using hardware components, often gathered from untrusted third-party vendors, to meet cost and time-to-market constraints. These hardware components may have vulnerabilities, which an attacker can exploit to leak secret information or cause system malfunction. While researchers have proposed many promising ideas to detect pre-silicon vulnerabilities, the existing solutions are not useful for fabricated chips (referred to as “”post-silicon”” stage), since it is not possible to observe or analyze all the internal signals. Moreover, it is infeasible to detect a wide variety of vulnerabilities during fabrication and/or validation (at the “”pre-silicon”” stages) due to runtime and other constraints. Post-silicon security validation will enable secure and trustworthy systems. The impacts of this project are to develop highly secure SoCs through synergistic integration of pre-silicon verification with post-silicon security validation, working closely with industry to enable technology transfer and produce results with practical significance, and training students of diverse backgrounds for the workforce.

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