Tag: Yier Jin

Resilient and Robust High Performance Computing Platforms for Scientific Computing Integrity

As technology advances, computer systems are subject to increasingly sophisticated cyber-attacks that compromise both their security and integrity. Recent research has highlighted that high performance computing platforms are vulnerable to these attacks. This situation is made worse by a lack of fundamental security solutions that both perform well and are effective at preventing threats. High performance computing platforms used in commercial and scientific applications involving sensitive, or even classified, data are frequently targeted by powerful adversaries. Current security solutions fail to address the threat landscape or ensure the integrity of sensitive data. As challenges grow in this area, both private and public sectors are expressing the need for robust technologies to protect computing infrastructure. Novel solutions hardening high performance computing platforms without loss of performance or energy efficiency are being developed by Dr. Jin and his research group. Advancing the state-of-the-art in high performance computing research, Dr. Jin is developing fine-grained memory protection that is scalable, adaptive, and lightweight to enhance intrusion detection and is addressing the threat landscape facing high performance computing environments. Dr. Jin’s work offers optimized, secure, and efficient solutions that will keep pace with security and user demands for both current and future platforms. Dr. Jin’s research helps the Department of Energy achieve its mission of providing secure exascale computing platforms to the scientific community.

Medium: Security Certification of Autonomous Cyber-Physical Systems

With the observation that a thorough security certification of autonomous CPS will provide formal evaluation of autonomous CPS, the researchers in this project intend to develop methods to facilitate manufacturers for certifying security solutions. Toward this goal, the researchers will first develop new theories to understand the impact of physical and cyber-attack on system level properties such as controllability, stability, and safety. They will then develop algorithms for detection and recovery of CPS from physical attacks on active sensors. The proposed recovery method will ensure the integrity of sensor measurements when the system is under attack. Furthermore, a new analysis framework will be constructed that uses platform-based design methodology to represent the CPS and verifies it against design metric constraints such as security, timing, resource, and performance. The key contributions of this project towards autonomous CPS security certification include 1) a comprehensive study of relationship between attacks and system-level properties; 2) algorithms and their optimization for detection and automatic recovery of autonomous CPS from attacks; and 3) systematically quantifying impact of security on design metrics.

RESULTS: Reverse Engineering Solutions on Ubiquitous Logic for Trustworthiness and Security

This project develops an automated trustworthiness and security analysis framework to help end-users address their concerns by reconstructing the behavioral description of commercial-off-the-shelf ICs and analyzing such description for functionality identification and detection of design flaws and/or potentially inserted hardware Trojans and backdoors. This tool suite offers an all-in-one technology to allow engineers to quickly go from physical circuit structure/netlists to behavior/specification and validate the security and trustworthiness of any digital ICs, through data-path and state register identification, state transition graph construction and decomposition, data flow recovery, high-level behavioral design reconstruction, and whitelist- and blacklist-based functionality determination and hardware Trojan/backdoor detection. As a Transition to Practice (TTP) project, the research team is also closely collaborating with an industrial partner in developing, integrating, and validating the tool suite, so that a holistic and practice-oriented hardware security tool suite is provided for protecting the IC supply chain.