Growing complexity of system-on-chip (SoC) and ever-increasing cost of IC fabrication have forced the semiconductor industry to shift from a vertical business model to a horizontal model. In this model, time-to-market and manufacturing costs are lowered through outsourcing and design reuse. To be more specific, SoC designers obtain licenses for third party intellectual property (3PIPs), design an SoC by integrating the 3PIPs with their own IPs, and then outsource the SoC design to contract foundries and assemblies for fabrication, test and packaging. With most of these entities involved in design, manufacturing, integration, and distribution located across the globe, original IP owners no longer have the ability to monitor the entire process. The lack of trust and transparency/control has led to vulnerabilities such as IP piracy, IC overproduction, cloning, tampering, and more. To protect the supply chain from such vulnerabilities, academic and industry researchers have proposed many techniques e.g., IP encryption, logic obfuscation, secure split test, etc. However, recent literature have pointed out to some of the limitations of these approaches. In this webinar, we will present complementary techniques to provide an end-to-end solution to protecting electronic supply chain.