Scott E. Thompson was an Intel Fellow, Director of Logic Technology and responsible for next generation process integration, technology yield and transistor design from 1992 to 2004. Thompson joined Intel in 1992 and has worked on Intel’s 0.35, 0.25, 0.18, 0.13 and 0.09 – micron advanced CMOS logic technologies. Thompson and co-workers were the first to publish at the International Electron Device Meeting (IEDM) in 2002 on a 90nm logic technology which introduced high levels strain for significant mobility enhancement using SiGe. This 90nm strained Si logic technology is currently in production on 300mm wafers to fabricate all of Intel’s advanced microprocessors. Thompson has published 60 papers and holds 12 patents all relating to transistor design. Scott was elected IEEE Fellow for his contributions on submicron and nanoscale MOSFETs.
Thompson’s current research interest are on advance transistors focusing on Strained Si and Ge channel MOSFETs, carbon nanotube transistors and nanotechnology.