ECE Seminar: RISQrypt: Fast, Secure, and Configurable HW/SW Co-Design for Post-Quantum Cryptograph

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Erkay Savaş received the BS (1990) and MS (1994) degrees in electrical engineering from the Electronics and Communications Engineering Department at Istanbul Technical University. He completed the PhD degree in the Department of Electrical and Computer Engineering (ECE) at Oregon State University in June 2000. He had worked for various companies and research institutions before he joined Sabanci University in 2002. He has been the dean of Faculty of Engineering and Natural Science, Sabanci University, since July 1, 2020. His research interests include applied cryptography, data and communication security, privacy in biometrics, security and privacy in data mining applications, embedded systems security, and distributed systems. He is a member of IEEE, ACM, the IEEE Computer Society, and the International Association of Cryptologic Research (IACR).

As the transition to post-quantum cryptography accelerates, the need for high-performance and side-channel-resistant hardware architectures has become more critical than ever. This seminar introduces RISQrypt, a RISC-V–based hardware/software co-design framework that delivers fast, secure, and configurable acceleration for leading post-quantum cryptographic standards — CRYSTALS-Kyber (key encapsulation) and CRYSTALS-Dilithium (digital signature). RISQrypt achieves this through a unified architecture that integrates dedicated arithmetic units and hardware countermeasures to ensure resilience against side-channel attacks, while maintaining flexibility across cryptographic primitives. Its scalable Number Theoretic Transform (NTT) engine supports multiple moduli and parameter sets, enabling efficient adaptation to various lattice-based schemes. The design offers a portable, fast and energy-efficient foundation for secure embedded and IoT platforms. The seminar will present the architectural design principles, co-design methodology, and implementation results of RISQrypt on FPGA platforms. Performance and security metrics will be compared with existing state-of-the-art accelerators, demonstrating significant improvements in throughput, configurability, and side-channel resistance. The talk will conclude with future directions, including energy-aware optimization, multi-scheme scalability, and integration into post-quantum secure processors.